In semiconductor devices such as ASICs and FPGAs, there is known a phenomenon where, even when the same circuits are mounted on devices of the same type, outputs that differ from one device to another are obtained because of the difference among individual devices in device characteristics such as a gate delay. A circuit that causes such phenomenon or a technology therefor is called “physical unclonable function” or “physical uncloning technology” (in the following description, this technology is referred to as “PUF”), and such technology is expected to be applied to authentication, encryption, and other usages.
As an example of the PUF, there is known a related art that uses a glitch generated in an output signal of a combinational circuit (see, for example, Patent Literature 1). FIG. 13 are a diagram illustrating a basic configuration of a PUF (hereinafter referred to as “glitch PUF”) disclosed in Patent Literature 1 and explanatory diagrams of specific signal processing. A glitch PUF 1301 illustrated in FIG. 13(a) includes a data register group 1320, a glitch generation circuit 1330, and a bit conversion circuit 1340.
The glitch as used herein is a phenomenon where the value of a signal is changed repeatedly between 0 and 1 with intensity, which is observed in a transitional state where the value of the signal is changing. A peak generated in a signal waveform is also referred to as “glitch”.
In FIG. 13(a), when the value of an input signal 1311 to the glitch generation circuit 1330 formed of the combinational circuit is changed, the value of an output signal 1312 changes accordingly. The glitch is generated in the transitional state, which lasts until the change is completed. A signal including the glitch is hereinafter referred to as “glitch signal”.
The glitch changes depending on the characteristics of the individual device on which the glitch generation circuit 1330 is mounted. In other words, even when the same glitch generation circuit 1330 is used, the glitches generated by the respective devices differ from one device to another. In view of this, bits that differ from one device to another can be generated by determining the value of 0 or 1 in accordance with the shape of the glitch. The value may be determined by, for example, the following method. Specifically, in the method, the value is determined as 0 when the number of peaks included in the glitch is an even number and the value is determined as 1 when the number of peaks is an odd number.
FIG. 13(b) illustrates the above-mentioned flow of bit generation processing performed by the glitch PUF 1301. FIG. 13(c) illustrates a mounting example of processing of converting the glitch shape into a bit performed by the bit conversion circuit 1340. FIG. 13(c) illustrates the bit conversion circuit 1340 that uses a toggle flip-flop (hereinafter referred to as “toggle FF”) and a timing chart of its operation.
The toggle FF is a circuit in which when a rising signal is input once, an output value is inverted (changed to 0 when being 1 and changed to 0 when being 1). With this principle, whether the number of peaks included in the glitch is an even number or an odd number corresponds to whether the number of times of output inversion is an even number or an odd number on a one-to-one basis, and as a result, corresponds to whether the bit value is 0 or 1 on a one-to-one basis.
Through the series of processing illustrated in FIG. 13, one bit is generated so as to correspond to each input signal 1311. A bit sequence having a plurality of bits can be generated by performing this processing a plurality of times while varying how the input signal 1311 is changed. Specifically, when the input signal to be input to the glitch generation circuit 1330 has n bits, for example, the bit sequence having 2n−1 bits can be generated by changing the input signal 2n−1 times, that is, 0→1, 0→2, . . . , 0→2n−1.